paging in AMD64

[diurpaneus]

Hello,
I'm trying to understand the AMD64 paging mode by following Stephanvanschaik/Setting Up Long Mode tutorial at: http://wiki.osdev.org/User:Stephanvansc ... _Long_Mode. But I can't understand how to setup the PML4E field.
According to the AMD64 Manual, volume 2 at page 131: bits 51 to bits 12 represent the pointer to the base of the PML3 table. So I was expecting the first PML4 entry to be: 0x2000003. But in his tutorial he sets the first entry to 0x2003( bit 0 and bit 1 are the P and R/W flags). The tables are located at:
PML4 0x1000
PML3 0x2000
PML2 0x3000
PML1 0x4000
Can someone explain why the PML tables are setup like this?

[Combuster]

bits 12..48 match bits 12..48 of the address (and not 36..0). There's no point in storing 12 zeroes when each pagetable must be page aligned - instead those 12 bits are used as flags.