I-32e Paging problem

[prinzrainer]

Just after setting the PG bit, there was a strange behavior.
Bochs' sayd something like this: "No linear - physical translation for addresss"
I've tried using "info tab" in bochsdbg. I was surprised that pages are mapped differently from
what I've expected. See below.

I am using BOCHS-2.4.1

Mappings info:
Address-Value
0x100000 - (quad) 0x0000000000101003 ; PML4->(PDPT @ 0x101000),P,R/W
0x101000 - (quad) 0x0000000000000138 ; PDPTE->(1GiB Page @ 0G),P,R/W,PS,G
0x101008 - (quad) 0x0000000040000138 ; PDPTE->(1GiB Page @ 1G),P,R/W,PS,G
0x101010 - (quad) 0x0000000080000138 ; PDPTE->(1GiB Page @ 2G),P,R/W,PS,G
0x101018 - (quad) 0x00000000C0000138 ; PDPTE->(1GiB Page @ 3G),P,R/W,PS,G

Cpu:
CR0 - 0xe0000011 ; PG,CD,NW,ET,PE
CR2 - 0;
CR3 - 0x00100000 ; PML4 @ 0x100(000)
CR4 - 0x000000a0 ; PGE,PAE
EFER - 0x00000500 ; LMA,LME

I have no idea of what the problem is.

[Tosi]

Most likely a problem in your page allocator.

[Combuster]

Not sure what you are trying to demonstrate with your custom dump, but the numerical dump says all of the address space is marked non-present while the other half of your dump says they are. (same concern holds for the writable and user bits)

Also, why is PSE off, and have you checked your emulated processor supports 1G pages?

[prinzrainer]

Not sure what you are trying to demonstrate with your custom dump, but the numerical dump says all of the address space is marked non-present while the other half of your dump says they are. (same concern holds for the writable and user bits)

oh, its:
0x101000 - (quad) 0x0000000000000183 ; PDPTE->(1GiB Page @ 0G),P,R/W,PS,G
0x101008 - (quad) 0x0000000040000183 ; PDPTE->(1GiB Page @ 1G),P,R/W,PS,G
0x101010 - (quad) 0x0000000080000183 ; PDPTE->(1GiB Page @ 2G),P,R/W,PS,G
0x101018 - (quad) 0x00000000C0000183 ; PDPTE->(1GiB Page @ 3G),P,R/W,PS,G

instead of 138...sorry..

I found out that bochs doesn't support 1GiB pages...so I turned to 2MiB pages and it works fine.
It seems that the PSE bit on cr4 determines only the for 4MiB PSE capabilities for 32-bit paging, doesn't it?
So how do I know really know if the processor support 2MiB PSE capabilities?

[a5498828]

pse bit in control register is only for 32 bit paging. in pae its ignored, PS bit in paigng table is never ignored.
read the manual please, its all there.

[prinzrainer]

pse bit in control register is only for 32 bit paging. in pae its ignored, PS bit in paigng table is never ignored.
read the manual please, its all there.

That's what I'm telling you. Intel doesn't seem to tell how to identify support of 2MiB pages (in I-32e).. Since PS bit on cr4 is only for 32bit paging...

[Hangin10]

*edit: not relevant*

[prinzrainer]

I meant 2MiB pages....

[Combuster]

The relevant part of the manual:

The size of large pages in PAE-paging mode is 2 Mbytes rather than 4 Mbytes. PAE uses the pagedirectory page-size bit (PDE.PS) to allow selection between 4-Kbyte and 2-Mbyte page sizes. PAE automatically uses the page-size bit, so the value of CR4.PSE is ignored by PAE paging.

[prinzrainer]

The relevant part of the manual:

The size of large pages in PAE-paging mode is 2 Mbytes rather than 4 Mbytes. PAE uses the pagedirectory page-size bit (PDE.PS) to allow selection between 4-Kbyte and 2-Mbyte page sizes. PAE automatically uses the page-size bit, so the value of CR4.PSE is ignored by PAE paging.

So in I-32e, 2MiB pages is always supported?

[gravaera]

Did you read the manual to see?