[RESOLVED] CPU reset on interrupt with higher half kernel

[Tosi]

I have a higher half kernel that is loaded at 0x00100000 which is mapped to virtual 0xC0100000.
It sets up a GDT with a flat address space and IDT before initializing paging.
I know I have the GDT and paging set up correctly
because I can do a lot of other things before issuing the interrupt, including printing to the screen
and detecting some hardware. However, when I try an "int $0x00" the CPU triple faults immediately.
I have tried using both logical and virtual addresses for vectors in the IDT, but neither worked.
Bochs reports the GDT and IDT like this.

Code: Select all

gdtr:base=0x00103006, limit=0x17
idtr:base=0x00102008, limit=0xff

This looks correct, since those are physical addresses instead of virtual ones.

Here are some relevant lines from Bochs' log:

Code: Select all

00079450127-d-@c01004fd-[CPU0 ] interrupt(): vector = 00, TYPE = 4, EXT = 0
00079450127-d-@c01004fd-[CPU0 ] page walk for address 0x0010300e
00079450127-d-@c01004fd-[CPU0 ] PDE: entry not present
00079450127-d-@c01004fd-[CPU0 ] page fault for address 0010300e @ c01004fd
00079450127-d-@c01004fd-[CPU0 ] exception(0x0e): error_code=0000
00079450127-d-@c01004fb-[CPU0 ] interrupt(): vector = 0e, TYPE = 3, EXT = 1
00079450127-d-@c01004fb-[CPU0 ] page walk for address 0x0010300e
00079450127-d-@c01004fb-[CPU0 ] PDE: entry not present
00079450127-d-@c01004fb-[CPU0 ] page fault for address 0010300e @ c01004fb
00079450127-d-@c01004fb-[CPU0 ] exception(0x0e): error_code=0000
00079450127-d-@c01004fb-[CPU0 ] exception(0x08): error_code=0000
00079450127-d-@c01004fb-[CPU0 ] interrupt(): vector = 08, TYPE = 3, EXT = 1
00079450127-d-@c01004fb-[CPU0 ] page walk for address 0x0010300e
00079450127-d-@c01004fb-[CPU0 ] PDE: entry not present
00079450127-d-@c01004fb-[CPU0 ] page fault for address 0010300e @ c01004fb
00079450127-d-@c01004fb-[CPU0 ] exception(0x0e): error_code=0000

It appears that it's trying to read a physical address as a virtual one for whatever reason,
but even when I put virtual addresses in my IDT it repots this.
Does anybody have an idea as to what could be going wrong?

[gerryg400]

The GDT and IDT must contain virtual addresses.

[Tosi]

Wow.
The Intel manuals said that GDTR and IDTR used physical addresses, or at least that's what I inferred. They were always kind of hazy on that.
Thank you very much gerryg400.

[Combuster]

There are three kinds of adresses possible: virtual, linear and physical. segmentation maps virtual addresses to linear addresses, and paging maps linear addresses to physical addresses. Since most people use only the paging mechanism, it is a common error to distinguish virtual from linear = physical addresses because it is a natural guess to make.

Needless to say, the manuals say that IDT, GDT, LDT and TSS have linear starting addresses, which is usually the same as the virtual address, not the pysical address.

[Tosi]

Now I get my problem. For some reason, I thought paging mapped virtual addresses to linear addresses, and then segmentation maps the resulting linear address to a physical address. I had the entire order addresses were translated backwards! Thanks for setting me straight, it will solve lots of problems in the future now.
In my old kernel I could get away with assuming things like that because of the simpler memory model I used, now I must be more careful.