Error in IDT wiki article

[crazy2k]

Hello. I found a small error in the IDT article in the wiki. IDTR's base field is a linear (not physical) address. Also, Is it correct what it says about bits 0..2? And shouldn't size be sizeof(idt) - 1?

Thanks,

[crazy2k]

Oh, I just realized those fields are in the register, and they're not necessarily the same the structure you have in memory and load using lidt has. Anyway, in the "Loading/Storing" section, it says the offset is "the virtual address of the table itself", and it should say "linear".

Thanks,

[gerryg400]

IDTR's base field is a linear (not physical) address.

Correct, it's linear, not physical, not segment relative.

Also, Is it correct what it says about bits 0..2?

No, I don't think so. All bits would be needed especially since the limit will always be an odd number I think.

And shouldn't size be sizeof(idt) - 1?

Yes, meaning the limit is always odd.

[Nable]

And at least one more thing: in the article we can read that non-present entry causes #GPF but if we look into AMD manual vol2 chapter 8.2.12 we'll see:

An #NP occurs when an attempt is made to load a segment or gate with a clear present bit, as described
in the following situations:
...
- Referencing a gate descriptor containing a clear present bit.