Safe handling of ICR register in Apic

[rdos]

The Intel software manual is not specific about how to handle the ICR, when it is busy, and how long it could potentially remain busy. It doesn't say if there is any buffering either (are new writes lost if the busy flag is set?)

Possible multithreading/ISR safe handling of ICR:

Code: Select all

icr_send:
    cli
    test ICR,DeliveryStatusBit
    jz icr_ready
    sti 
    pause
    jmp icr_send

icr_ready:
    mov ICR+4,edx
    mov ICR,eax
    sti

Would this always work even if IPIs are sent in ISRs / directly after each others?