Is the IDT accessed via MMU address translation?

[Armin]

Hi all,

when I enable paging in my OS, I first map my kernel 1:1 (physical to virtual addresses) and then I map my kernel to the virtual base address 0xC0000000 and finally I unmap the 1:1 kernel mapping. The problem is that when I remove the 1:1 kernel mapping (I set the corresponding pages to "not present" in the page table), Interrupts are not working any more.

According to my understanding, I thought Interrupt handling is not affected by paging at all, because the IDT is accessed via physical addresses. So any kernel mapping should not play a role for interrupt handling. But in my kernel, it seems, as if a 1:1 mapped kernel is necessary in order to access the IDT.

Does anyone know how it really works resp. what could be the error here?

Thanks in advance.

[gerryg400]

IDT is accessed by virtual address. You will need to reload the IDT, GDT etc after enabling paging if your mapping is not 1:1

The only odd thing is that lgdt and lidt access linear (non-segmented) address. But since most segments are zero-based this doesn't matter.

- gerryg400