Hi i am trying to implement ochi usb and am having trouble getting it initialized.
i was wondering if there was a source code example out there somewhere
I have read through the wiki and the ohci document but i am still confused how to get the endpoint descriptors to process.
have tried many different ways but I cant seem to get it to process.
I wont post code at the moment because it is a bit of a mess.
Any help appreciated
Shredded
usb ochi tutorial/example
Re: usb ochi tutorial/example
We have implemented a well-working EHCI driver and are currently working at USB. Perhaps we can support each other.
http://www.c-plusplus.de/forum/viewforu ... is-62.html
irc.euirc.net #PrettyOS
http://www.c-plusplus.de/forum/viewforu ... is-62.html
irc.euirc.net #PrettyOS
http://www.henkessoft.de/OS_Dev/OS_Dev3.htm (OSDEV)
http://www.c-plusplus.de/forum/viewforu ... is-62.html
irc.euirc.net #PrettyOS
http://www.c-plusplus.de/forum/viewforu ... is-62.html
irc.euirc.net #PrettyOS
Re: usb ochi tutorial/example
Thanks for the reply.
I am interested in getting usb working for a memory stick to save files on.
My system currently boots off CD. and have some UDF/Atapi stuff working.
I have been checking your forum link and some of the content looks interesting
shredded
I am interested in getting usb working for a memory stick to save files on.
My system currently boots off CD. and have some UDF/Atapi stuff working.
I have been checking your forum link and some of the content looks interesting
shredded
Re: usb ochi tutorial/example
Hi again I have got my code communicating with the ohci and thought i would post it for anyone who is interested.
just a couple of things that i will mention
1. Condition code in TD needs to be set to 111x binary on entry {found this in bochs log}
2. RAX is set to the value of BAR0 from the PCI on entry to Init
3. I am using 64bit code, will work on 32bit but you will have to change registers
4. This code is just to test communication with usb and has not yet been developed into a fully functioning driver
5. Memory is mapped 1:1 in page tables remember to map the address that BAR0 points too.
Ok thats all.
Shredded
just a couple of things that i will mention
1. Condition code in TD needs to be set to 111x binary on entry {found this in bochs log}
2. RAX is set to the value of BAR0 from the PCI on entry to Init
3. I am using 64bit code, will work on 32bit but you will have to change registers
4. This code is just to test communication with usb and has not yet been developed into a fully functioning driver
5. Memory is mapped 1:1 in page tables remember to map the address that BAR0 points too.
Ok thats all.
Shredded
Code: Select all
;/////////////////////////
; initiate OHCI usb
baseAddr dq 0x00
HcFMInt dd 0x00
init:
mov [baseAddr],rax ;base address passed in rax
mov rdi,[baseAddr] ;store
add rdi,0x34 ;HcFMInterval
mov eax,[rdi]
mov rdi,HcFMInt
mov [rdi],eax
mov rdi,[baseAddr]
add rdi,0x08
mov eax,[rdi]
or eax,0x08 ;request owner change
mov [rdi],eax
call delay
mov rdi,[baseAddr]
add rdi,0x04
ownerLoop:
mov eax,[rdi]
bt rax,8 ;check if IR {Interupt Routing} is cleared
jc ownerLoop
mov rdi,[baseAddr]
add rdi,0x08
mov eax,[rdi]
or eax,0x01 ;reset HC
mov [rdi],eax
call delay
;----------------
mov rdi,[baseAddr] ;HcFMInterval
add rdi,0x34 ;as Set by BIOS/SMM
mov eax,[HcFMInt]
mov [rdi],eax
;----------------
mov rdi,[baseAddr]
add rdi,0x04
mov eax,[rdi]
mov ebx,0xffffff2f
and eax,ebx
or eax,0x00 ;USB_RESET dont need <OR> but reads better
mov [rdi],eax
mov rsi,[baseAddr] ;new hcca address
add rsi,0x18
mov rax,0
mov eax,0x81000
mov [rsi],eax
mov rsi,[baseAddr] ;RESET PORT 1
add rsi,0x54
mov eax,0x10
mov [rsi],eax
call delay
mov rsi,[baseAddr] ;power
add rsi,0x54
mov eax,0x100100
mov [rsi],eax
call delay
mov rdi,[baseAddr]
add rdi,0x14
mov eax,0x80000040 ;disable interupts
mov [rdi],eax
call delay
mov rdi,[baseAddr]
add rdi,0x04
mov eax,[rdi]
mov ebx,0xffffff20
and eax,ebx
or eax,0x90 ;USB_OPERATIONAL & Control List
mov [rdi],eax
call delay ;seems to require this delay
call delay ;will replace with timer {sleep function}
mov rdi,[baseAddr]
add rdi,0x54
mov eax,0x02
mov [rdi],eax ;Enable USB 1
call setupPacket
call delay
mov rdi,[baseAddr]
add rdi,0x08
mov eax,[rdi]
or eax,2 ;set Control List Filled
mov [rdi],eax
call delay
mov rdi,0xb83c0 ;vidmem
mov rsi,0x804a0 ; buffer
mov rcx,0x12
devlp:
call printbyte ;prints DEVICE descriptor
add rdi,6
inc rsi
dec rcx
cmp rcx,0
jnz devlp
ret
;//////////////////////
;/ print Byte
printbyte:
mov al,[rsi]
shr al,4
and al,0xf
cmp al,10
jl pblt
sub al,10
add al,0x41
jmp pbnxt
pblt:
add al,0x30
pbnxt:
mov [rdi],al
mov al,[rsi]
and al,0x0f
cmp al,10
jl pblt2
sub al,10
add al,0x41
jmp pbnxt2
pblt2:
add al,0x30
pbnxt2:
mov [rdi+2],al
ret
;//////////////////////
; setup packet
pk2 db 0x80,0x06,0x03,0x01,0x00,0x00,0x12,0x00 ;get DEVICE descriptor
pk3 db 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff ;set data to known state
db 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff ;used only for debugging
db 0xff,0xff
ed1 dd 0x82000
dd 0x803a0 ;tail
dd 0x80200 ;head
dd 0x00 ;next ED
td1 dd 0xf0e00000
dd 0x80480 ;00
dd 0x80300
dd 0x80487 ;07
td2 dd 0xf0f00000
dd 0x804a0 ;00 + output Buffer {pk3}
dd 0x80380
dd 0x804a7 ;07
td3 dd 0xf0f00000
dd 0x804a8 ;08
dd 0x80390
dd 0x804af ;0f
td3a dd 0xf0f40000
dd 0x804b0 ;10
dd 0x803a0
dd 0x804b1 ;11
td4 dd 0
dd 0
dd 0
dd 0
setupPacket:
push rax
push rdi
push rcx
push rsi
mov rsi,pk2
mov rdi,0x80480
mov rcx,16
rep movsb
mov rsi,pk3
mov rdi,0x804a0
mov rcx,18
rep movsb
mov rsi,ed1
mov rdi,0x80100
mov rcx,16
rep movsb
mov rsi,td1
mov rdi,0x80200
mov rcx,16
rep movsb
mov rsi,td2
mov rdi,0x80300
mov rcx,16
rep movsb
mov rsi,td3
mov rdi,0x80380
mov rcx,16
rep movsb
mov rsi,td3a
mov rdi,0x80390
mov rcx,16
rep movsb
mov rsi,td4
mov rdi,0x803a0
mov rcx,16
rep movsb
mov rdi,[baseAddr]
add rdi,0x20
mov eax,0x80100
mov [rdi],eax ;HcControlHead
add rdi,4
mov [rdi],eax ;HcControlCurrent
pop rsi
pop rcx
pop rdi
pop rax
ret
;/////////////////////
; short delay
delay:
mov rcx,0xfffff
dellp:
dec rcx
cmp rcx,0
jnz dellp
ret
Re: usb ochi tutorial/example
how about change.
ed1 dd 0x82000
dd 0x803a0 ;tail
dd 0x80200 ;head
dd 0x00 ;next ED
td1 dd 0xf0e00000
dd 0x80480 ;00
dd 0x80300
dd 0x80487 ;07
td2 dd 0xf0f00000
dd 0x804a0 ;00 + output Buffer {pk3}
dd 0x80380
dd 0x804a7 ;07
to.............
ed1 dd 0x122000
dd 0x803a0 ;tail
dd 0x80200 ;head
dd 0x00 ;next ED
td1 dd 0xf0e40000
dd 0x80480 ;00
dd 0x80300
dd 0x80487 ;07
td2 dd 0xf0f40000
dd 0x804a0 ;00 + output Buffer {pk3}
dd 0x803a0
dd 0x804b1 ;11
ed1 dd 0x82000
dd 0x803a0 ;tail
dd 0x80200 ;head
dd 0x00 ;next ED
td1 dd 0xf0e00000
dd 0x80480 ;00
dd 0x80300
dd 0x80487 ;07
td2 dd 0xf0f00000
dd 0x804a0 ;00 + output Buffer {pk3}
dd 0x80380
dd 0x804a7 ;07
to.............
ed1 dd 0x122000
dd 0x803a0 ;tail
dd 0x80200 ;head
dd 0x00 ;next ED
td1 dd 0xf0e40000
dd 0x80480 ;00
dd 0x80300
dd 0x80487 ;07
td2 dd 0xf0f40000
dd 0x804a0 ;00 + output Buffer {pk3}
dd 0x803a0
dd 0x804b1 ;11