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Today I just wanted to do some benchmarks on my AMD K6-3 400 cpu and my code didn´t work. So I searched for the problem and it seems either I´m too dumb to read the specifications or AMD did not what they were saying in the specs.
So in the specs stands for the sysret instruction:
Bits [63–48]+1000b of the STAR register specify the selector that is copied into the SS register.
Bits [1–0] of the SS register are set to 11b (RPL of 3) regardless of the value of bits [49–48] of the STAR register.
So if I understand this right, if I loaded a value of 0x18 into [63-48] of the STAR register the values which are written to cs and ss are 0x1B (=cs) and 0x23 (=ss). The value for cs is right, but for ss the cpu only writes 0x20 into the register which was the source of my problem. So to fix this "bug" (??) I only needed to write 0x1B into [63-48] of the STAR register.
My question now is, is this a known bug and does anyone know if this is the same behavior on later amd cpus or if I´m just too dumb to read the specs? And will this work on later amd cpus (at the moment I have no possibility to test it on later amd cpus)?
AMD manual wrote:In both cases, the CPL is forced to 3, effectively ignoring STAR bits 49–48. The SS selector is updated
to point to the next descriptor-table entry after the CS descriptor (STAR.SYSRET_CS + , and its RPL is not forced to 3.
I blame the version of the manual
"Certainly avoid yourself. He is a newbie and might not realize it. You'll hate his code deeply a few years down the road." - Sortie
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