16bit ISA DMA on actual hardware

[bewing]

I would like to know if anyone here has ever tested -- or even if anyone HAS available to test -- any 16bit ISA DMA boards?

Specifically, I would like a firm answer to the question: is it actually possible to transfer 128Kb in a single transfer, or is the max really 64K? Yes, I know what the wiki says -- but there are at least 5 mistakes in the wiki article and I'm about to rewrite it anyway. The theory is that if you set up a 128K transfer: it actually transfers the same 64K twice, on a read -- or overwrites the first 64K with the second on a write. The possible hardware solution would be to shift the address registers up one bit for 16bit DMA ... but I don't know if this was done ... I see no mention of such a thing anywhere.

In a previous thread Brendan was recalling that the max is really 64K. From what I've read recently, I think he's right. But he wasn't sure, and I'm not sure.

So, has anyone tested it on real hardware? Or is there some real hardware to test?

[Brendan]

Hi,

I would like to know if anyone here has ever tested -- or even if anyone HAS available to test -- any 16bit ISA DMA boards?

I've probably got some ISA sound cards that use 16-bit ISA DMA, but I'm not sure I've got adequate programming information for them.

Specifically, I would like a firm answer to the question: is it actually possible to transfer 128Kb in a single transfer, or is the max really 64K? Yes, I know what the wiki says -- but there are at least 5 mistakes in the wiki article and I'm about to rewrite it anyway. The theory is that if you set up a 128K transfer: it actually transfers the same 64K twice, on a read -- or overwrites the first 64K with the second on a write. The possible hardware solution would be to shift the address registers up one bit for 16bit DMA ... but I don't know if this was done ... I see no mention of such a thing anywhere.

I went digging. The original documentation for the "DMA chips" is useless because it depends on how the chip is wired into the rest of the system. I found an answer in more recent Intel chipsets (in the "PCI to LPC bridge" section).

The following is from Intel's "Intel® 82801BA I/O Controller Hub 2 (ICH2) and Intel® 82801BAM I/O Controller Hub 2 Mobile (ICH2-M)" datasheet, from "9.2.1 DMABASE_CA—DMA Base and Current Address Registers" on page 9-24:

Base and Current Address—R/W. This register determines the address for the transfers to be performed. The address specified points to two separate registers. On writes, the value is stored in the Base Address register and copied to the Current Address register. On reads, the value is returned
from the Current Address register.
The address increments/decrements in the Current Address register after each transfer, depending on the mode of the transfer. If the channel is in auto-initialize mode, the Current Address register will be reloaded from the Base Address register after a terminal count is generated.
For transfers to/from a 16-bit slave (channels 5–7), the address is shifted left one bit location. Bit 15 will be shifted out. Therefore, if bit 15 was a 1, it will be lost.
The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop.
Before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first.

If I understand correctly, this means that if you attempt to transfer 128 KiB then the second 64 KiB will be a repeat of the first 64 KiB because the "current address" register's highest bit gets shifted out.


Cheers,

Brendan

[bewing]

Thanks Brendan!
What a difference 11 little words make, eh? I agree with your interpretation. If bit 15 is "lost" and not "ORed" or "ORed then shifted" -- then 128Kb transfers are out.
I will be rewriting the wiki article now.