Cannot get periodic APIC timer interrupt

[torshie]

I follow AMD's system programming guide and try to enable APIC timer. I only the a one-shot interrupt, although I set bit 17 of the APIC timer register.
This is my APIC initialization code, and the attached is a screen shot of qemu. The line "APIC Tick: 1" is from my timer interrupt handler. What is wrong with my initialization code?

Code: Select all

InterruptController::InterruptController() {
	Processor& processor = getProcessorInstance<Processor>();
	Address physical = processor.getModelSpecificRegister(MSR_APIC_BASE_ADDRES_REGISTER);
	physical = (physical >> 12) << 12;
	PageMap::embedPhysicalMemory(physical, CONTROLLER_BASE_ADDRESS, PAGE_SIZE);
	Message::brief << "APIC ID: " << Register<APIC_REGISTER_ID>::reference() << "\n";
	Message::brief << "APIC Version: " << Register<APIC_REGISTER_VERSION>::reference() << "\n";
	U32& initialCount = Register<APIC_REGISTER_TIMER_INITIAL_COUNT>::reference() ;
	U32& timer = Register<APIC_REGISTER_ENTRY_TIMER>::reference();
	U32& timerDevideConfig = Register<APIC_REGISTER_TIMER_DIVIDE_CONFIGURATION>::reference();
	timerDevideConfig = 10;
	initialCount = 0xffffff;
	timer = InterruptDescriptorTable::APIC_INTERRUPT_TIMER | (1 << 17);
	for (;;) {
		volatile int i = 0;
		Message::brief << "Timer: " << timer << " Initial Count: "
				<< Register<APIC_REGISTER_TIMER_CURRENT_COUNT>::reference() << "\n";
		for (; i < 100000000; ++i) {
		}
	}
}

Cheers

--torshie

[torshie]

BTW, I already tried add volatile before U32& and disable cache, nothing difference.

[Seed]

Do you send an EOI signal in your timer interrupt handler?

[torshie]

Do you send an EOI signal in your timer interrupt handler?

Thanks for replying. I do forgot...