cyrix cpus (6x86)

[FlashBurn]

Does anyone have some documentation about the 6x86 cyrix cpus? I need a explanation of the device registers to enable the cpuid instruction and some other things.

[Combuster]

The documentation is somewhere on the web, but it's notoriously hard to find

Unless someone knows where to find a copy, I can put mine online when I get back home.
In the meantime, you can look up some stuff from my Cyrix initialisation code (and you'll probably want this too)

[FlashBurn]

Thanks, I searched for the cyrix documentation, but only found some code. I also have a document how to enable the cpuid instruction, but I don´t like to write some magic values to some magic ports w/o knowing what they mean.

[Combuster]

Long story short, cyrix uses a hack to access model-specific registers: if you write port 22 hex, then access port 23 hex directly afterwards, it will access the MSR instead of accessing the bus. Writes to port 22 are therefore not serialized. I have yet to find anything else at that address though...

Anyway, you can read and write MSRs that way. You have a few containing model and revision (DIR = device identification register), and a few configuration registers. Cyrices with CPUID have a DIR0 >= 0x30 (model 3).
CCR3 (chip control register 3) contains a lock bit (bit 5) for most other registers. you set it to get access to all MSRs rather than a small subset. CCR4 contains the CPUID bit (bit 8 ), you'll probably want to set that one too.

I hope that's enough explanation? (because my memory on the matter is rather rusty)

[FlashBurn]

I couldn´t test my code yet, but it would be helpfull if you could upload the documents somewhere. I also recall that there was a cache option like the old k5/k6 had it (write allocation or so) and for this I would also need the documentation.

[Brendan]

Hi,

I couldn´t test my code yet, but it would be helpfull if you could upload the documents somewhere. I also recall that there was a cache option like the old k5/k6 had it (write allocation or so) and for this I would also need the documentation.

For a complete summary of "useful things", there's:

• - CPU identification for older CPUs (that don't support CPUID)
  - enabling CPUID for newer CPUs
  - an "allow L1 cache write misses to cause a cache line allocation" enable/disable flag (to improve L1 cache hit rates)
  - a "suspend on HLT" enable/disable flag to reduce power consumption (at the expense of IRQ handling latency) when HLT is used
  - an "allow page directory entries to be cached" enable/disable flag that is meant to improve performance when page tables are modified frequently
  - an "ignore the LOCK prefix" enable/disable flag that might improve performance for software that is designed for multi-CPU but is running on single-CPU (but might also cause problems with bus mastering/DMA race conditions in badly designed drivers in specific cases).
  - a "slow down LOOP" enable/disable flag. This is funny, as some idiots used "LOOP $" to measure very short time delays and Cyrix optimised the LOOP instruction so that it's a lot faster, which caused problems in software written by idiots (e.g. (old versions of?) 3D Studio). This flag allows you to make LOOP slower to get around the idiot's mistake.
  - a way to fix the Cyrix "Coma" bug, so CPL=3 code can't lock up the CPU
  - "Region Control Registers" which do the same thing as MTRRs on Intel CPUs

Most of this stuff may or may not be present, depending on exactly which Cyrix CPU it is (5x86, 6x86, etc); and the default state of some of it probably depends on which BIOS you're using (e.g. you don't know if the BIOS has enabled or disabled the "slow loops" feature, etc).

Unfortunately Cyrix documentation is a little hard to find now (as Cyrix died and their CPUs are consider obsolete now). Probably the best way to find it is to go to Sandpile's documentation page and copy each document's title (and/or file name) into a search engine. If you have trouble I might be able to email the documentation I've collected; although to be honest I'm not too sure about the legalities (do copyright laws apply when the copyright holder is a company that doesn't exist anymore? Unfortunately, it might be the same as a deceased human copyright holder, where copyright still applies).


Cheers,

Brendan

[Brynet-Inc]

Unfortunately Cyrix documentation is a little hard to find now (as Cyrix died and their CPUs are consider obsolete now). Probably the best way to find it is to go to Sandpile's documentation page and copy each document's title (and/or file name) into a search engine. If you have trouble I might be able to email the documentation I've collected; although to be honest I'm not too sure about the legalities (do copyright laws apply when the copyright holder is a company that doesn't exist anymore? Unfortunately, it might be the same as a deceased human copyright holder, where copyright still applies).

According to Wikipedia they were bought out by VIA, presumably that means all "IP" is theirs.. including former documentation released by Cyrix.

Probably similar to "abandonware", it's in legal limbo.. the current owners are unaware of it, or simply choose not to do anything with it, like how Palm keeps BeOS in an attic.

I'd guess it's safe for nostalgic end users.. I doubt that any self respecting company would engage in litigation.

IANAL, I just stole some guys suit.

[FlashBurn]

@brendan

As I think this documentation was available for everyone before this should be no problem and there is also code which everyone can look at from where you can get some info (but not all).

As for the useful things, there are somethings I would like to get my hands on and as I´m only supporting the 6x86mx (because I need the PSE and TSC feature) somethings should be no problem. So if you willing to send me the documents you have it would be nice. Maybe I should write a mail to VIA for asking to get this documentation or if it is allowed to put this documentation online?!

[FlashBurn]

I have 3 Cyrix cpus here and all say that they don´t support PSE, but in 1 document of Cyrix stands that it supports PSE till the 6x86MX. Does anyone know if the documentation is wrong there or if I have cpus which aren´t supporting it, but there are cpus out there that support it?