EBP register questions

[~]

It looks like the Intel manuals say that that if we use something like

Code: Select all

mov eax,[bp]
mov eax,[ebp]
mov eax,[ebp+10]

then the default segment register to be used will be SS, so the code above, at least in 16-bit Real Mode, by default would be the same as

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mov eax,[ss:bp]
mov eax,[ss:ebp]
mov eax,[ss:ebp+10]

Now is that correct? And if so, does it work by default in the same way in 32 and 64-bit modes?





At least I think that's why my Unreal Mode was freezing when using [ebp] values greater than 0xFFFF with an SS segment limit of 0xFFFF (it's said that limits for SS and CS shouldn't be changed from that value for use in 16-bit mode, be it Real or Unreal).

[thepowersgang]

Well, in 32-bit and 64-bit modes, SS is still used, but since usually a flat segmentation model is used SS == DS.
As to why your unreal mode code doesn't work, that could be why, but that should cause some form of fault that would trap to the BIOS and reset the machine (I think)

[Combuster]

As the intel manuals state, using SP/ESP/RSP or BP/EBP/RBP will by default use SS rather than DS. That behaviour is unrelated to anything unreal mode related.

The thing with 64kb CS and SS values in real mode is a different thing. It makes little sense to have CS > 64k as IP will be 16 bit, and execution will theoretically wrap around to the start of CS. (Intel suggests it will crash and burn instead) The same holds for SS, as interrupts will treat the stack as 16 bits, similarly causing the stackpointer to ignore the top 16 bits, making any stack address > 64k pointless.

[Owen]

In Long Mode, ANY value goes for DS/SS/ES as long as the SPL is set correctly. Upon entering an ISR, the processor will even NULL SS when an interrupt results in a privilege level change! Since all the bits of a data segment descriptor are ignored in Long mode, this is of no consequence.

FS and GS will continue to load the 32-bit base (zero extended) from the GDT; the OS can write to the FS and GS MSRs to load a full 64-bit base, and the SWAPGS instruction will swap the GS base MSR's contents with the system GS base MSR's contents. The last feature is often used to get access to per CPU or per process information following a SYSCALL, with another SWAPGS occurring before returning to user mode.

(Loading a DS/ES/SS value past the end of the GDT or LDT may or may not cause a GPF, I haven't looked into this)