16-bit protected mode?

[junkoi]

Hi,

I am still confused on the concept of the 16-bit protected mode.

Is it true that:
- This mode is similar to 16-bit real-mode, except that protected feature (CR0, bit 0) is turned on?
- Does it still use segment:offset to to access to memory, in which segment is limited to 64KB?

Where can I find more information on this mode?

(Yes, I have the Intel manual, but that is hard to digest, with a lot of irrelevant mixed information about various mode put in to the same doc...)

Thanks,
Jun

[XanClic]

Does it still use segment:offset to to access to memory, in which segment is limited to 64KB?

No, it uses the same addressing mode as 32 bit protected mode does, though every entry in the GDT is limited to 64 kB.

Is it true that this mode is similar to 16-bit real-mode, except that protected feature (CR0, bit 0) is turned on?

No, at least because of the new addressing mode that allows you to access 16 MB of memory (the base address of every GDT entry (in 16 bit protected mode) is 24 bits long).

Sorry, but I don't know where you could find more information on that topic... Maybe Wikipedia is worth trying.

[qw]

Intel 80286 Programmer's Reference Manual 1987

Roel

[Gigasoft]

On 80386 and newer processors, 16-bit protected mode means using 16-bit as the default operand and address sizes by turning off bit 54 in the code and data segment descriptors. That's all it is. Otherwise it's exactly the same.

Bit 54 of a code segment descriptor (called the D bit) sets the default operand and address size to 32 bits, and bit 54 of a data segment descriptor (called the B bit) sets the stack pointer size to 32 bits when using instructions that implicitly access the stack. The stack pointer size can not be overridden.

Usually, the default size is set to 16 bits when the majority of instructions use 16 bits operands and addressing, and 32 bits when most instructions use 32 bits operands and addressing.

16-bit addressing modes are the same as in real mode, and the resulting address has the high order word cleared. 32-bit addressing modes can use any base register and any index register except ESP, and index registers can be scaled.

[Love4Boobies]

There are also some differences with the TSS - can't remember which but I can look them up if it's really important. Unfortunately the current Intel manuals won't help you much if you want to write code that will work on the 16-bit pmode Intel 286 has to offer. I'd look into the document Hobbes linked to.

[Combuster]

No, it uses the same addressing mode as 32 bit protected mode does, though every entry in the GDT is limited to 64 kB.

Yes and no. The 286 was still limited to 16 bits, and in its version of protected mode, the limit field was limited to 16 bits, and the offset to 24 bits, making the segment size 64K max and giving access to 16MB of memory.
The 386 extended practically everything from 16 to 32 bits, including the base and limits (although only 20 bits of the limit can be directly programmed), and added a setting to default to 32-bits rather than 16. This is all backwards compatible.

The question is, are you referring to protected mode running with a default size of 16 bits (where you can still access all 4GB the same way you would in unreal mode), or the 286 implementation of protected mode which actually has all the mentioned limitations?
In other words, do you want to write code for the 286?