Speed Regression when using PCI IDE

[pcmattman]

Hi everyone,

I recently implemented support for the PIIX's IDE interface so that I could work with DMA in the ATA/ATAPI driver. I have it working now, with DMA and all, but it seems to be around about three times slower then the conventional ISA + PIO method. This slowdown happens in QEMU and VirtualBox (have not tested other emulators).

I have configured the IDETIM register (possibly incorrectly?) and saw no improvement. Even when DMA is disabled, standard port I/O is still significantly slower when using the PCI IDE interface. I'm pretty much at a loss here, and the spec isn't giving any answers at the moment.

Any ideas?

[Combuster]

Emulators are really bad things to test speed of hardware I/O on. One way or another the data must be transferred from HD to memory. DMA is the equivalent of another processing core in a system, which in emulation contexts means that the time normally spent on one core (CPU) has now to be spent on two (CPU+DMA).

Also, using port I/O is faster since the data does not need to make extra detours. The only reason why DMA is used is that it releases that time for other tasks, giving an overall in throughput at the cost of latency. Obviously, that extra throughput is only attained when there is something to "put through".

If you test, make your tests as fair as possible. An emulator is not a fair comparison.

[pcmattman]

I see what you're saying, but I did mention that I have run a test without DMA at all:

Even when DMA is disabled, standard port I/O is still significantly slower when using the PCI IDE interface

If, and only if, the PCI IDE interface has been active, PIO runs at the same speed. Only by removing the PCI IDE interface and just probing the ports for devices can I get significant speed improvements in an emulator.

I just don't understand why adding that extra layer is causing such a significant slowdown. Perhaps I've mis-interpreted the spec somewhere, I don't know. You can see the code here, maybe that'll shed some light on the situation.

[Combuster]

Ah. Guessed you had something else on your mind.

Try thinking of a way for software to emulate a TLB for a multitude of PCI bars with various sizes and offsets, both IO and memory-mapped, while taking care of overlap, address forwards to different buses, northbridge controls, etc etc...

Anyway, the fact that emulators suck for proper speed testing still holds