Setting Up Paging [CR3, Flags, Assembly] [Little Guidance]

[jaswax]

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[Hangin10]

You don't need to set anything else in CR3 besides the address of the page directory.
In particular, bits 0 and 1 are reserved. Check the layout of the control registers in the intel manuals (in the slightly older hardcopy I have at hand, Section 2.5 has a nice figure of CR0-4).

A few things about your assembly code:
You can XOR a register with itself to make it zero, smaller instruction, and easier on the eyes. When you are setting entries in the tables, why not start with 0x3? Why shuffle the values around to avoid it, adding 0x1000 to a number never alters the 0x3 at the end.

[jaswax]

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[Hangin10]

When you add to EDI to get to the next entry, you're only adding one. These entries are 4 bytes long. Also, you don't necessarily know what is going to be in CR3, so you should really just move the value into a register, and then put that into CR3.

I should have seen that the first time. Shows how well I think in assembly!
Why not just use C? It seems like you would have had things working by now.

[jaswax]

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[geppyfx]

this code appears to be correct to me but I haven't tested it

Code: Select all

     mov   ecx, 1024
   mov   edi, 0x701000        ;address of the page table
   mov   ebx, 3               ;set attributes to present and read/write
.npte:
   mov   [edi], ebx           ;write the data to memory
   add   edi, 4               ;go to next memory location
   add   ebx, 4096
   dec   ecx
   jnz   .npte

  ;make all PDEs not present by default
   cld
   xor   eax, eax
   mov   ecx, 4096/4
   mov   edi, 0x700000
   mov   ebx, edi             ;to save bytes later
   rep   stosd
   
   mov   dword [ebx], 0x701003    ;set 1st PDE to point to PT
   mov   cr3, ebx

   mov   eax, cr0
   or    eax, 0x80000000
   mov   cr0, eax              

[jaswax]

Deleted

[Hangin10]

If it's outside of any segment, you can't access it.

Any writes (except ones that use ESP/EBP for a base) use the data segment by default.

The GDT needs to be mapped in.
The base address of the GDT in the GDTR is virtual if paging is on.

So my two questions for you are:
1) Is your kernel being identity mapped?
2) Why are all of your segments not base zero and limit 4GB? (I don't know if you are trying to do something that involves a segmented memory model, but just making everything flat is way easier.)

[jaswax]

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[stlw]

I think that I am just going to go back to my little cave and hide.

I really don't understand paging. I understand segmentation and could split memory up into segments until the cows come home.
So where to go from here?

I won't be mad if there are no replies. Thanks to all who tried to help.

You told you using emulator. Are you using Bochs ? So why don't just quote its messages when tripple faulting ?
If you enable debug:report instead of debug:ignore you will get much more verbose paging messaging as well.

Stanislav

[jaswax]

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[Combuster]

Regarding questions 1..4, I really recommend that you look up how virtual memory works (Paging, Segmentation, Intel software developer manual 3A), read some tutorials, then think about what *you* want. It's pretty useless to give suggestions right now when you are unlikely to understand the suggestions made.

For question #5, see the FAQ, although it is a bad idea to think about actually doing that while you haven't grabbed the basics...