"Conforms to bus" APIC polarity for NMI & ExtInt

[geppyfx]

How do you people deal with (IO/L)APIC polarity for NMI & ExtINT?
In MADT it simply says "Conforms to specifications of the bus". Must I assume that this the ISA bus that they are speaking about?
In MP Table they do give the bus # but is this a valid bus number? Because why would NMI come from isa or pci bus only?

[mathematician]

Traditionally, channel 0 of the DMA Controller was hardwired to the processor's NMI pin, so that an NMI was generated if your memory chips were frying (ISA bus). In later versions of the AT there was a failsafe timer, which could also trigger a non maskable interrupt. Nowadays you can nominate any interrupt you want for treatment as an NMI.

The PCI bus only "owns" four interrupt lines. In theory you can find out what they are by scanning PCI configuration space to see which lines individual devices are connected to.

In the olden days there was a one to one correspondence between hardware devices and the IRQ lines they were connected to, and everything was nice and simple. Now it's a mess. Hopefully the advent of message signalled interrupts will help to sort the mess out.

[geppyfx]

I am adding ExtInt for mixed mode(if MP present) until I manage to understand AML, and adding NMI.
High polarity seem to work for now but planning to add Low polarity testing if high doesn't appear to work. Will try to trigger an interrupt with both polarities.

[mathematician]

ISA interrupts are edge triggered, active high. PCI interrupts are level triggered, active low.

[geppyfx]

You apparently insist that extInt & nmi should be treated as they are from isa bus. Good.