Paging breaks descriptor tables

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computafreak
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Posts: 76
Joined: Sun Dec 14, 2008 1:53 pm

Paging breaks descriptor tables

Post by computafreak »

I've got a set of most peculiar problems with my kernel. They seem to be broken up into three. First of, my memory allocation function seems to be broken. When I zero out a structure created by a page-aligned memory allocation function, I also zero out another, unrelated variable. My memory allocation code is below, where placementAddress initially is equal to the end of the kernel, and align is whether to page-align the memory (set here to true)

Code: Select all

if(placementAddress % 0x1000)
		placementAddress += 0x1000 - (placementAddress % 0x1000);
	if(align && (placementAddress & 0xFFFFF000))
    {
        placementAddress &= 0xFFFFF000;
        placementAddress += 0x1000;
    }
    if(physicalAddress)
        *physicalAddress = placementAddress;
    placementAddress += size;
    return placementAddress - size;
My second problem is that when I write the new (ORed by 0x80000000) CR0 value, I break my GDT and IDT - Bochs says that the GDT points to invalid memory; I assume that the IDT is broken because I get an unhandled page fault exception when I have explicitly set one up. When I break into the debugger immediately after the exception, CR0 has the paging bit set; I think that this means something broken got accessed by the invalidate page instruction, suggesting in turn that the page tables are broken. The third problem is the page fault exception itself - it occurs immediately after the LEAVE instruction, but I cannot go any further in terms of debugging until I can get a proper IDT set up

My kernel is based upon James Molloy's tutorials, but I've gone through line-by-line and nothing seems different except for a different IRQ0. Either way, it isn't set up when I activate paging. My Bochs log is attached, if it helps
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bochsLog.txt
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computafreak
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Posts: 76
Joined: Sun Dec 14, 2008 1:53 pm

Re: Paging breaks descriptor tables

Post by computafreak »

A quick update. I've found the problem with my memory allocation - I had misplaced a bracket!

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uint MemoryAccess::placementAddress = (uint)&end & 0xFFFFF000 + 0x1000;
became

Code: Select all

uint MemoryAccess::placementAddress = ((uint)&end & 0xFFFFF000) + 0x1000;
. However, my second and third problems remain. My memory isn't identity mapped for some reason - it maps 0x10400000->0x1050FFFF to 0x0->0x0010FFFF, adding 0x10400000 to every memory location. This keeps the IDT and GDT firmly out of reach. The instruction at which the page fault occurs is still the same. I've uploaded my paging and memory access code - could someone look over it, see where I'm going wrong please?
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Paging.cpp
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Memory.cpp
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computafreak
Member
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Posts: 76
Joined: Sun Dec 14, 2008 1:53 pm

Re: Paging breaks descriptor tables

Post by computafreak »

I've solved the second problem. I had got some structure declarations messed up. I was also not page-aligning my page tables, which didn't seem to help. Identity mapping is set up successfully. Now I simply have a page fault when I STI; my IDT and GDT are actually working now. My registers are below:

CR0: 0xE0000011: PG CD NW ac wp ne ET ts em mp PE
CR2: 0x208F0010
CR3: 0x0010e000
PCD=page-level cache disable=0
PWT=page-level writes transparent=0
CR4: 0x00000000: osxsave smx vmx osxmmexcpt osfxsr pce pge mce pae pse de tsd pvi vme
EFER: 0x00000000: ffxsr nxe lma lme sce
rax: 0x00000000:00106286
rcx: 0x00000000:00000004
rdx: 0x00000000:000003d5
rbx: 0x00000000:00106900
rsp: 0x00000000:00108eec
rbp: 0x00000000:00108f24
rsi: 0x00000000:00108fbc
rdi: 0x00000000:00108f6c
r8 : 0x00000000:00000000
r9 : 0x00000000:00000000
r10: 0x00000000:00000000
r11: 0x00000000:00000000
r12: 0x00000000:00000000
r13: 0x00000000:00000000
r14: 0x00000000:00000000
r15: 0x00000000:00000000
rip: 0x00000000:001050e6
eflags: 0x00000002
eax: 0x106286
ebx: 0x106900
ecx: 0x0
edx: 0x3D5
esi: 0x108FBC
edi: 0x108F6C
ebp: 0x108F24
esp: 0x108EEC
eip: 0x1050E6
End of kernel: 0x10A000
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