IRQ 0 in Bochs
-
- Member
- Posts: 524
- Joined: Sun Nov 09, 2008 2:55 am
- Location: Pennsylvania, USA
IRQ 0 in Bochs
Although this hasn't yet created a problem, does anyone know what IRQ 0 (in the IO APIC, not the legacy PIC) is in Bochs? I'm assumming it is a timer, it keeps on firing every 10000 instructions or so.
Re: IRQ 0 in Bochs
it changes.
Sometimes 0 == IRQ 0 (PIT)
and sometimes 1 == IRQ 0
you need to create a translation function to change from an ISA interrupt to an IOAPIC redirection entry. (use the MP/ACPI tables to get BUS ID's and interrupt pins/bus numbers).
Sometimes 0 == IRQ 0 (PIT)
and sometimes 1 == IRQ 0
you need to create a translation function to change from an ISA interrupt to an IOAPIC redirection entry. (use the MP/ACPI tables to get BUS ID's and interrupt pins/bus numbers).
Website: https://joscor.com
-
- Member
- Posts: 93
- Joined: Mon Nov 24, 2008 9:13 am
Re: IRQ 0 in Bochs
Do you mean the input 0 of the I/O APIC? In Bochs in many other real hardware configurations it is the output of the legacy PIC.JohnnyTheDon wrote:Although this hasn't yet created a problem, does anyone know what IRQ 0 (in the IO APIC, not the legacy PIC) is in Bochs? I'm assumming it is a timer, it keeps on firing every 10000 instructions or so.
That's to provide compatibility to old system software that doesn't know about APICs. The BIOS configures therefore a system with APICs in the PIC mode or in Virtual Wire Mode a/b. (See MP Spec.) If "Virtual Wire Mode via I/O APIC" is implemented the legacy PIC's output is routed to an input of an I/O APIC. In the according "Redirection Table Entry" the input is configured to be "ExtINT" - that means, the interrupt request would be forwarded to the CPUs (over the APIC bus/system bus), but the acknowledging CPU has to ask for the interrupt vector. At the time the CPU asks for the vector, the legacy PIC will provide the vector. So the I/O APIC is just used as a virtual wire to forward the interrupt request.
In many systems the vendors chose to use input 0 of the only I/O APIC for this "ExtINT" thing. But to keep things simple they identity mapped iSA-IRQ x to input x of the I/O APIC. Only ISA-IRQ 0 could not be assigned in this way. Because ISA-IRQ 2 is for the 8259A cascading and not used for everything else, input 2 of the I/O APIC is free. So they connect ISA-IRQ 0 (the PIT) to input 2 of the I/O APIC.
But that is not true for every system. The vendors can choose to implement it very, let's say, "freaky". So you have to work it out, what is connected where. The MP tables help you doing this. ACPI tables also have some information, but when it comes to interrupts originating from PCI and which are not routed to ISA-IRQs (like Bochs/Qemu do it), you may be in trouble. This information is only provided in the DSDT, which is AML code, that you have to parse with an AML interpreter. That's a *huge* pain to do. (You could use ACPICA though, that will save you many "tears", but this way you will have a lesser learning outcome.)
Regards,
Thilo