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Hi,
I'm trying to setup paging with PAE enabled (2MB pages). As soon as the paging is turned on, the system restarts. Any idea on what's going on? The AMD CPU has PAE support. I checked the cpuid and feature flags already. I've seen people mapping the the last page dir entry in 4KB non-PAE paging. If that is required here, how is it done?
- Thanks in advance
Try adding the 'hlt' instruction after the first instruction in paging_on. If it doesn't crash but instead hangs, then move it to after the next instruction, and so on. The first time it does crash, the hlt instruction will be right after the faulty instruction.
CodeCat wrote:Try adding the 'hlt' instruction after the first instruction in paging_on. If it doesn't crash but instead hangs, then move it to after the next instruction, and so on. The first time it does crash, the hlt instruction will be right after the faulty instruction.
Or, use a suitable debugger, like the Bochs one. Much easier.
__inline void paging_on(void *pdp)
{
__asm__ __volatile__(
/* Load the page table address */
"movl %0, %%cr3\n\t"
/* Enable pae */
"movl %%cr4, %%eax\n\t"
"orl $0x20, %%eax\n\t"
"movl %%eax, %%cr4\n\t"
/* Enable paging */
"movl %%cr0, %%eax\n\t"
"orl $0x80000000, %%eax\n\t"
"movl %%eax, %%cr0\n\t"
"hlt \n\t" <====== system resets just before this point
:
: "r" (pdp)
: "ax"
);
}
I inserted 'hlt' after every instruction and the reset happens after enabling paging. This paging_on() stub is taken from the popular memtest http://www.memtest86.com/ . The problem could be that I'm doing something wrong wrt the page-dir-ptr. My system has only 1GB physical memory and I guess it should be ok to enable PAE. Any help will be appreciated very much.
Thanks again
-sawdust