Initial TSS Size Question

[indiocolifa]

I've setup a proper GDT for my OS (Kernel CS/DS and User Mode CS/DS) and added a TSS recently for hardware context switches.
The thing I can't catch (yes, i've looked in the Intel manuals) is about the limit and granularity fields of the TSS descriptor in the GDT. I've put my TSS at 0x23000 linear address with a limit of 1KB and 1-byte granularity, since I understood that above the 0x67 default size of TSS you can put IOPL permission bitmap, I think 1024 bytes will do the trick.

Another question is: since my kernel is top-half design, can I refer the TSS base as e.g 0xC0001000 now (before entering PM at the OS loader)?
Any additional tips on how to setup the TSS?

[JohnnyTheDon]

No. Before entering PM or switching to the code segment set up for higher half, all addresses are physical. You must access it with a physical address. I recommend (though this isn't required) that you build the TSS after you load the GDT and enter the higher half kernel. This simplifies everything, and it is always a good idea to do as little as possible before you enter protected mode.