I'm not 100% sure about these answers, but...
chezzestix wrote:What would happen if your GDT placed a section at the 3gig mark and the user only had 2gig? What happens to the latter half of the 2 gig data section if a gig is missing?
It'll only cause problems when you access the missing memory with the (unless virtual memory is in use).
chezzestix wrote:When two sections overlap which DPL is followed?
GDT Tutorial wrote:// Selector 0x10 will be our data
I think you've misunderstood something about the GDT - the value in CS, DS, ES, FS, and GS (the segment selectors) is the index of an entry in the GDT. If CS = 0x08, it would execute code with the base/limit, attributes, and the DPL specified by the second entry (more description on this is in the Intel Manuals). Since only one section/GDT entry is the one used to govern the memory accesses, which is specified by the value provided in CS/DS (of course, this entry is different for code and data), DPLs can't overlap. The selector 0x10 points to the 3rd index of the GDT, which would define a data segment.
chezzestix wrote:Both the setups explained in the GDT tutorial seem sketchy to my under informed brain. Flat setup especially has no restrictions anywhere in the memory. Meaning that ring 0 data is stored next to and can be accessed by user level programs. Shouldnt some sections be set up for 0-2 ring only access? Or is there something in paging that is going to protect my kernel's stacks from open corruption?
That's the purpose of segmentation and paging. It's generally not a good idea to do one flat memory space if you want memory protection. Segmentation allows you to define separate segments which cover separate sections via separate selectors. Paging allows you to virtualize a blank memory space (you can pretend to have 4GB for each application when you only have 16MB of RAM) for each application, so that it can't interfere with the kernel or other applications.