Question about which tools to use, bugs, the best way to implement a function, etc should go here. Don't forget to see if your question is answered in the wiki first! When in doubt post here.
There is TF(bit 8 ) in 80X86 CPU.
I can't understand its use.
I think it maybe has relations with Int 01h.
Interrupt Jump Table wrote:
Int 01 - CPU-generated - SINGLE STEP
Int 01 - CPU-generated (80386+) - DEBUGGING EXCEPTIONS
Volume 3A_ System Programming Guide wrote:
TF Trap (bit 8 ) : Set to enable single-step mode for debugging; clear to
disable single-step mode. In single-step mode, the processor generates a
debug exception after each instruction. This allows the execution state of a
program to be inspected after each instruction. If an application program
sets the TF flag using a POPF, POPFD, or IRET instruction, a debug exception
is generated after the instruction that follows the POPF, POPFD, or IRET.
you have to provide your own ISR routine for it to do anything usefull.
when this gets called you will have on top of stack the cs:ip of the instruction to be executed, which you can modify, etc. its good for single step debugging.
df wrote:you have to provide your own ISR routine for it to do anything usefull.
when this gets called you will have on top of stack the cs:ip of the instruction to be executed, which you can modify, etc. its good for single step debugging.
What is the number of my own ISR? int 1h or other?
You can change any Interrupt to whatever you want by changing there entry in the IVT/IDT (Depending on what mode you're in...), so change INT 1 to whatever you want, the point of the TF is to have an interrupt that can give you tailored more targeted debug info for every single operation....
Jules