Paging, am i right ??

[kmtdk]

Hei

well after reading a lot of Paging, also from intels dead borring manul, i got this picture in my head:
first you activate paging using the last bit in cr0.

Then mov the address of the page dir table into cr3. the rest bis is for options about paging.

the dir table is pointing to a page table, or page tables, whitch are pointing to a page, or pages.

well

am i right, or totaly lost
if am right ( sorry for asking stuppid)
what to do after setting up.

Thanks

[suthers]

I personally put the address of the page in cr3 first, then I set the paging bit in cr0, but it might work the other way round, but the page tables don't only contain the address of the pages, but also their attributes.
Jules

edit: P.S. I never tested it because of other bugs in my kernel....

[kmtdk]

yea....
so Iam not totaly lost, but what to do after setting all of this up ????

Thx

[suthers]

After you done all of that paging is enabled...
Nothing else to do...
Jules

[kmtdk]

hmm
well
how to remap the address, because that point have I Not figured out.

Thanks

[suthers]

I have no idea right now, when I tried to implement it, I didn't get any further than that when I tried to implement it... and a quick look around reveals that there aren't any tutorials on it, so you'll have to use docs....
I'll try and do it myself and post what I find, if somebody hasn't done it first (I'm sure there are quite a few members of this forum who have already done it)....
Jules

P.S. I looked at the Intel docs on it and they are REALLY hard going, I'm in the process of translating it into easily intelligible language...

[geppy]

hmm
well
how to remap the address, because that point have I Not figured out.

Thanks

Protected mode:
you write 32bit physical address of any 4KB block into Page-Table entry(EDIT: and make sure virtual address points to this page-table entry)

virtual address contains indexes of Directory entry, Page-Table entry & offset within 4KB(lowest 12bits)
32bit Directory entry contains address of the Page-Table table
CR3 contains physical address of the Directory table

in Page-Table entry lowest 12bits are used for flags so they are not necessary zero but in virtual address the bits used as offset within 4KB

EDIT: at the end of whole paging process CPU will take highest 20bits of page-table entry and combine them with lowest 12bits of virtual address. That will be physical memory location on your stick(s) of RAM where you data will be saved(or read).

[kmtdk]

after sitting an reading from the manual, i thing i got the ideer:

(page 112, the illustration!)

it take the first 10 bits of the Directory adress adress == 10 first bits from the Table page adress, and finaly 12 bits from the page's adress.

==========================
if not, then help me .

Thanks

(when i get this to work, i will write a little tutorial on this, in asm )

[Combuster]

Paging <- a lot of this is on the wiki

[kmtdk]

i have read that page, but it did not helped me that much.
but a littel.

Thx

[JamesM]

Hi,

Sorry for the plug, but it may possibly help you: Paging tutorial.

Cheers,

James

[kmtdk]

well
not realy.
I would just like to know if I was right about the calculation

anyway

THX

[geppy]

first 10bits of virtual address is entry number in Directory(its not address)
second 10 bits - entry # in page-table(its not address)
lowest 12bits is offset (its part of address)

each entry is 4baits so to get to that entry you need to multiply entry # by 4 and add address of the table itself

(virtual address = linear address)

[kmtdk]

can you give an example, so Im totaly sure, and understand the hole concept.


THX

[geppy]

Code: Select all

hex:      0xA73BE72E, this is linear(virtual) address 

           bits 31-22         21-12            11-0
binary:   1010011100   1110111110     011100101110b

1010011100b  =  668 decimal, entry #668 in Page-Directory
1110111110b  =  958 decimal, entry #958 in Page-Table
011100101110b = 0x72e

say physical addr of Page-Directory table in RAM is 0x200000 then CR3 has to be loaded with 0x200000
and physical addr of Page-Table table in RAM is 0x201000

ADDR_1 = physical addr of entry #668 = 668 * 4 + 0x200000
then you write 0x201000 to ADDR_1 so that Page-Directory entry #668 points to Page-Table (entire table)

ADDR_2 = physical addr of entry #958 = 958 * 4 + 0x201000
You write to ADDR_2 any memory address you like but it has to be aligned on 4KB boundary

If you write 0xC00000 (12MB) to ADDR_2 then every time you use addr 0xA73BE72E(around 2.61GB) – physical memory location 0xC0072E will be accessed


From your other thread:
- you don't calculate base address you pick one, any addr you like within physical RAM, and the addr has to be 4KB aligned
- linear address is also chosen at your will, but when you use it it has to point to valid physical memory using paging structures.