Access core1, core2, core3 in Quad

[Polygon]

Hello!
About 20 years ago, I did quite a bit of assembly coding for government projects, and became interested in BIOS design and modification about 4 year ago. Over the last 2 years, I have produced many successful BIOS to squeeze every ounce of performance out of enthusiast built systems.....

My latest project is with the new Phenom quad CPU. This is my 1st multi-core project. Also never worked on multi-node systems. I have read the AMD Kernel and BIOS Designers Guide cover-to-cover for the A64, AM2, and AM2+ CPU's, but have missed something somewhere..

My question has to do with setting up the other 3 cores at boot. In particular the registers that are in each core, like the MSR registers for example. How do I access a MSR for another core, from the boot core?

My guess is thru APIC and or SMM interrupts. Any help is greatly appreciated.

Thanks in advance!

[Cemre]

Hello,

for programming other cpus at boot:
here has an explanation of accessing multiple cpus.
AFAIK multi-core, hyper-thread and multiple cpu architectures do not differ in terms of programming.

http://www.osdever.net/tutorials/mp.php

you need to initialize the other cpu's through the local apic by sending
inter processor interrupt with "Interrupt Command Register" with DSH ( 11, all except self )

for accessing other cpus' internal registers, I don't know much.

[Polygon]

Thanks, I'll check it out!

[Combuster]

My question has to do with setting up the other 3 cores at boot. In particular the registers that are in each core, like the MSR registers for example. How do I access a MSR for another core, from the boot core?

Short answer: You can't.
Long answer: The only way to access all registers on a CPU is by running ring 0 code on them. So if you want to alter the registers on a different core, you must first manage to run code on that core that does it for you. inter-processor interrupts can help you doing that.

My guess is thru APIC and or SMM interrupts. Any help is greatly appreciated.

Local APIC interrupts indeed. SMM interrupts are mainly for bios use and not for multicore programming.

you need to initialize the other cpu's through the local apic by sending inter processor interrupt with "Interrupt Command Register" with DSH ( 11, all except self )

That's the quick-and dirty way. However, if IPIs get lost, then not all cores will wake up. Also, (less likely) the bios might have settings that tell certain cores not to be used. To make things more robust, you should read the ACPI tables and find out which cores are available to you, and then start them one at a time. (you may want to google for the intel multiboot specification)

[iammisc]

From what I can tell, the OP is writing a BIOS himself(is this right?). I think those who posted before me thought that he was writing an operating system.

I myself don't have much experience with multi-core processing but I just thought I'd point that out.

[Brendan]

Hi,

My question has to do with setting up the other 3 cores at boot. In particular the registers that are in each core, like the MSR registers for example. How do I access a MSR for another core, from the boot core?

My guess is thru APIC and or SMM interrupts. Any help is greatly appreciated.

Use the BSP CPU to setup the hypertransport links in all chips (the hypertransport links are made to look look like PCI devices AFAIK, and can be accessed directly from other CPUs). Then use the BSP to figure out almost everything else.

During boot the BIOS would send a broadcast "INIT-IPI, STARUP-IPI" sequence to the other CPUs to start them running, and each AP CPU would increment a "total CPUs present" counter. Once the AP CPUs are running the BIOS can use interlocking to control when the other CPUs execute pieces of initialization code (for e.g. code that initializes MSRs).

For example, imagine the AP CPUs do this:

Code: Select all

AP_startup_code:
   test eax,eax                  ;Did this CPU pass the BIST (Built In Self Test)?
   jne .die                      ; no, make sure no code uses it

   lock inc [totalCPUs]          ;Increase number of (usable) CPUs

   <stuff (setup protected mode??)>

   lock inc [myInterlock]

.APwait1:
   cmp dword [myInterlock],0
   jne .APwait1

   <more stuff (setup MTTRs and caching??)

   lock inc [myInterlock]

.APwait2:
   cmp dword [myInterlock],0
   jne .APwait2

   <even more stuff (add CPU to APCI and MPS tables??)>

   lock inc [myInterlock]

.die:
   cli
   hlt      ;Lock up (everything done)

Also imagine the BSP CPU is doing this at the same time:

Code: Select all

   mov eax,[totalCPUs]       ;eax = total CPUs present
   dec eax                   ;eax = total AP CPUs present

.BSPwait1:
   cmp [myInterlock],eax     ;Are all AP CPUs waiting to move to the next step?
   jne .BSPwait1             ; no, wait for them

   mov dword [myInterlock],0 ;Let AP CPUs move on to the next step

.BSPwait2:
   cmp [myInterlock],eax     ;Are all AP CPUs waiting to move to the next step?
   jne .BSPwait2             ; no, wait for them

   mov dword [myInterlock],0 ;Let AP CPUs move on to the next step

.BSPwait3:
   cmp [myInterlock],eax     ;Are all AP CPUs completed?
   jne .BSPwait3             ; no, wait for them

Of course you could use normal IPIs after the AP CPUs are started (but then you'd need to initialized local APICs, setup an IDT and possibly restore everything back to default after you're done).


Cheers,

Brendan

[Polygon]

Thanks! I'm taking this all in, and just haven't replied to every post. Thanks!

I am writing BIOS code and not OS code to answer a reply a few back....