[ATA] Reset & VMWare.

[Mikae]

Hello all.

During some tests of ATA devices detection and identification, I've found strange thing: after I reset devices on channel 1 in VMWare by setting and clearing SRST bit of device control register, DRDY bit of device 0 on the channel is never set. But if I remove code resetting the channel, problem with DRDY disappears. It happens only with channel 1, and there is no problem with channel 0.

Is it a problem of VMWare, or I have a bug in my code? I've wrote the simplest piece of code demonstrating the problem, could someone to look at it and to run it under VMWare:

Code: Select all

org 0x7C00

 xor ax, ax
 mov ds, ax
 mov es, ax
 mov ss, ax
 mov sp, 0x7C00

;Set SRST:
 mov dx, 0x376
 mov al, 0x4
 out dx, al

;Wait a little
 sti
 hlt
 hlt

;Clear SRST
 xor al, al
 out dx, al

;Wait again
 hlt
 hlt
 hlt
 hlt
 hlt
 hlt
 hlt
 hlt
 hlt
 hlt

;Select device
 mov dx, 0x176
 mov al, 0x0
 out dx, al

;Wait BSY
 mov dx, 0x177
.wait_BSY1:
 mov si, str_wait_BSY
 call print_str
 in al, dx
 test al, 0x80
 jnz .wait_BSY1

;Check DRDY
 mov dx, 0x177
 in al, dx
 test al, 0x40
 jz .error_DRDY
 mov si, str_ok_DRDY
 call print_err_str

.error_DRDY:
 mov si, str_error_DRDY
 call print_err_str

print_str:
.l00p:
 lodsb
 or al, al
 jz .exit
 mov ah, 0xE
 mov bx, 0x7
 int 0x10
 jmp .l00p
.exit:
 ret

print_err_str:
.l00p:
 lodsb
 or al, al
 jz .exit
 mov ah, 0xE
 mov bx, 0x7
 int 0x10
 jmp .l00p
.exit:
 jmp $

str_wait_BSY:   db 'Waiting BSY', 0xA, 0xD, 0x0
str_error_DRDY: db 'No DRDY', 0xA, 0xD, 0x0
str_ok_DRDY:    db 'DRDY Ok', 0xA, 0xD, 0x0

times 510 - ($ - $$) db 0xFF
dw 0xAA55

To disable channel resetting, comment out 'Set SRST' and 'Clear SRST' sections.

Configuration of my virtual machine is:
channel 0, device 0: ATA device
channel 0, device 1: empty
channel 1, device 0: ATAPI device
channel 1, device 1: empty
Version of VMWare is: VMWare Workstation 5.5.1 build-19175.

So, what may be the problem?..

TIA, Mikae.

[XCHG]

I suggest that you look at sections 9.3, 9.3.1 and 9.3.2 in ATA4 IDE Specifications that explain the sequences involved in a software reset of an ATA device. The explanation is really thorough. If you have problems understanding those, I will put my own code with comments and explanations in here.

[Mikae]

Thank you XCHG, I've found the answer on my question:

m) Setting DRDY:
1) If the PACKET command feature set is not implemented by Device 0, then the DRDY bit shall be
set to one within 30 s after the BSY bit has been cleared to zero. Steps (l) (1) and (m) (1) may
occur at the same time;
2) If the PACKET command feature set is implemented by Device 0, then Device 0 shall not set
DRDY to one;

It is very strange, but there is nothing about it in ATA/ATAPI-6-3b draft. So, moving to ATAPI is more complex than I thought -- ATAPI device doesn't depend on DRDY bit (at least, for IDENTIFY_PACKET_DEVICE command), so I have to add some additional check: if DRDY is not set, may be there is ATAPI device on the channel.