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hi there..
I have some simple questions that i want to clear out. In x86, When an IRQ interrupt happens, the cpu saves the return address on the stack of the interrupted process(correct me if i'm wrong). Then the ISR will run, which will save cpu context (anything else?), now the thing that i don't quite understand, where does the ISR put the saved data? on the ISR's stack, or on the interrupted process' stack?
Last Question, Does this whole process happen when traps, exceptions, aborts are triggered?
Hmmm, good question. I think an ISR is just a function and normally it is the function's job to save and restore the registers. So, it would be stored on the ISR's stack.
Yes, it does store this along with other "critical" information, like the instruction pointer and some segment registers.
The answer to your question depends on whether you're using hardware (aka TSS-based switching) or software task switching.
In hardware switching, the CPU performs a stack switch before the information is pushed to the stack, so it will end up on the ISR's stack.
In software task switching, the CPU doesn't do any sort of task switch on its own. Upon entry to the ISR, the CPU is still using the interrupted task's ISR. It is up to you to manage the stack.
"I have some simple questions that i want to clear out. In x86, When an IRQ interrupt happens, the cpu saves the return address on the stack of the interrupted process(correct me if i'm wrong)."
You're half wrong (see below)...
"Then the ISR will run, which will save cpu context (anything else?), now the thing that i don't quite understand, where does the ISR put the saved data? on the ISR's stack, or on the interrupted process' stack?"
If the interrupted code was running at ring 0 (priviliged mode), the ISR will use the interrupted process' stack. If the interrupted code was running at ring 3 (user mode), assuming the ISR is priviliged, the system will switch stacks before pushing anything, including the return address. It checks the current TSS for the appropriate stack settings (SS0:ESP0, usually) to determine where the ISR's stack will be.
