CR3 confusion

[C++arl]

Hi all!
I'm about to write a memory manager for my toy OS and have been googling some, but one thing is unlcear to me. Are all 32 bits of CR3 supposed to contain the address of the page directory, or only the 20 highest bits?

thx ~~ C++arl

[frank]

Well I believe that you use the whole CR3 register but I know that you have to align the page directory to 4kb so the bottom 12 bits of CR3 will be 0.

[Combuster]

Some of the bottom 12 bits have a special meaning. Commonly they are all zeroes, but two of the bits (PCD and PWT) can be changed to alter paging-related behaviour. The other bits are reserved and should be zero to avoid future compatibility issues.

@C++arl: read the intel/amd manuals first, next time.

[C++arl]

So that means that my page directory cannot reside at a address larger than 0xFFFFF and I dont see the logic in that since bits 5 - 11 appear to be unused . In my OS it would be logicall to place the PD at 0x102000, but i guess i'll have to rearrange things now.

[Combuster]

So that means that my page directory cannot reside at a address larger than 0xFFFFF

Didn't I just ask you to RTFM next time ?!

Table Base Address Field.
This field points to the starting physical address of the highest-level
page-translation table. The size of this field depends on the form of paging used:

• Normal (Non-PAE) Paging (CR4.PAE=0)—This 20-bit field occupies bits 31–12, and points to the base address of the page-directory table.
The page-directory table is aligned on a 4-Kbyte boundary, with the low-order 12 address bits (11–0) assumed to be 0. This yields a total base address size of 32 bits.

[JamesM]

Try this

[C++arl]

So that means that my page directory cannot reside at a address larger than 0xFFFFF

Didn't I just ask you to RTFM next time ?!

Table Base Address Field.
This field points to the starting physical address of the highest-level
page-translation table. The size of this field depends on the form of paging used:

• Normal (Non-PAE) Paging (CR4.PAE=0)—This 20-bit field occupies bits 31–12, and points to the base address of the page-directory table.
The page-directory table is aligned on a 4-Kbyte boundary, with the low-order 12 address bits (11–0) assumed to be 0. This yields a total base address size of 32 bits.

wtf is up your @$$, the manual? I read this manual: "IA-32 Intel Architecture Software Developer’s Manual Volume 3A: System Programming Guide, Part 1" and it said: "... Only the most-significant bits (less the lower 12 bits) of the base address are specified..." which made me a bit confused, so I decided to ask for some help on it. Got any problems with that, you 1337 haxx0rz n00b pwn3r or w/e you think you are.

@ JamesM: thx, thats the kind of supportive help i need .

[Candy]

wtf is up your @$$, the manual? <snip> Got any problems with that, you 1337 haxx0rz n00b pwn3r or w/e you think you are.

He's offering you help, you don't understand it but instead post a very rude offending comment back? Why would anybody bother helping you again?

Just food for thought.

[os64dev]

*snip*
Just food for thought.

Nah, just food for a ban as it is very offensive

[Combuster]

I read this manual: "IA-32 Intel Architecture Software Developer’s Manual Volume 3A: System Programming Guide, Part 1" and it said: "... Only the most-significant bits (less the lower 12 bits) of the base address are specified..." which made me a bit confused, so I decided to ask for some help on it.

With that bit of information I could tailor the answer to your needs, but in your previous posts you did not mention that, which left us to guess what you meant.

You said you looked over google. I wondered wether you found the manuals since they are pretty clear about that (if you see the images, you'll notice a reserved area and a writable area) given that you already knew the higher bits were supposed to be in place. Frank gave you a functionally correct answer, I added the bits he skipped over.
Next you post a reply that is in direct contradiction with your previously stated options, frank's post, and the excerpt from the (apparently intel) manuals you supposedly have read.
I see your reply, and I see two logical possibilities: either he found no decent source of information (the manuals) even after being pointed at it, or he suffers from some mental anomaly. Assuming good faith, I made obvious that the manuals are required reading and gave you the part that tells you everything you need to answer the question yourself. I might've overreacted a bit, but then again, there is a sticky that tells you everything.
And then it appears to be the manual itself you are confused about. Given that you didn't at all react to the part of my post to "read the manuals first, next time", It even strengthened my theory that you had indeed not read it.
Which brings us to that wonderful essay on "How to ask questions the smart way" - don't withold information and post what you have tried already. If you don't recall reading it, you should look it up again. (The section on screwups tells you that rtfm/stfw are the kind of replies that tell you that you did something wrong in asking the question)

As for your original question, The page directory can be anywhere on a 4k-aligned location. that means that any valid location has the bottom 12 bits set to 0. Since the designers of the intel processor want to be cheap with registers, they reused those 12 bits for other purposes. The way this currently happens means that valid locations for the PD are also valid values for CR3. the bottom 12 bits are kept in mind and when the location of the PD is computed, CR3 is accessed and instead of the special bits, 0s are supplied to generate the desired 32-bit address.

Oh and, I don't consider myself 1337, I only consider Brendan

[C++arl]

Reading through my previous post again, I realize i've been a a$shole, my apologies, its been a rough day

I am however of the opinion that one should be carefull with RTFM - it pisses ppl off, just a simple link to intel's website and a "its all in the manual" comment would do.

Anyway, just to straighten things out, the reason for my confusion is that the very manual i referr to contains a picture over CR3 where the bits lower than 20 are marked with 'Reserved'.

Yet again, I'm sorry for any hard words and do appreciate the help given, no beef i hope?

[os64dev]

The lowest 20 bits are reserved only in case of 2 MiB pages and the lowest 12 bits in case of 4 KiB pages. In case of 32 bit protected mode the upper bits contain the address of the page directory imposing the alignment by the reserved bits. So 2 MiB page tabled need to be aligned on 2 MiB pages and 4 KiB page tabled need to be aligned on 4 KiB pages. Very logical in a sence. But CR3 is always aligned to 4 KiB because the size of any of the paging table PML4E, PDPE, PDE or PTE is always 4 KiB even in long mode. Thus to answer your question: all 32 bits of CR3 contain the address of the page directory but due to the 4 KiB alignment only the highest 20 have meaning.
And therefore the intel ppl reused the lowest 12 bits for other purposes, but combuster explained that already.

[C++arl]

Thank you all very much, its completly clear to me now