GDT and such shared in multiprocessing?

[earlz]

ok, this is a weird question, and based on a question a friend asked me...
but I was thinking about it while going to sleep and it was driving me crazy!

so, when there are 2 or more CPUs, is the GDT shared between them? How is this possible though? if the GDTR is just a CPU register, then is the GDTR of the secondary(non-boot) cpu not used? Or is this something controlled in other hardware?

How is it that they can share their registers though? it just doesn't make sense as to how it is possible without special overrides...

[JAAman]

no, when you have 2 CPUs, each one has its own GDTR

each CPU must load the its GDTR with a LGDTR, but the GDT can be shared:

the GDT is not stored in the CPU -- it remains in memory at all times, only a pointer to it and the length of it is stored in the GDTR -- so both CPUs can share the same GDT, but each needs to load it into its own GDTR

its also possible to have a completely separate GDT for each CPU but thats not a requirement -- and since most people use a variation of flat mode, it is easier to simply use the same GDT and load the same pointer into each chip -- so you only have one GDT to manage

though you must be careful of changing entries when doing this -- it wont be updated on CPU that is currently using that entry, until it reloads the segment register, and if it does reload the segment register, it will be changed to the new entry -- but most people using flat models rarely (if ever) change the GDT at runtime, so it may not be an issue at all

[earlz]

hmmm...could it be possible to have one CPU running in protected mode, and the other running in (un)real mode? (that was my friends original question...)

with the TSS, wouldn't it be possible to have different TSSs for each cpu then? and with CR0 being seperate for CPUs, I don't see anything keeping you from it...

[frank]

hmmm...could it be possible to have one CPU running in protected mode, and the other running in (un)real mode? (that was my friends original question...)

with the TSS, wouldn't it be possible to have different TSSs for each cpu then? and with CR0 being seperate for CPUs, I don't see anything keeping you from it...

Yes the CPUs are completely separate entities. One can be in real mode while the other is in protected mode and so on.

Your supposed to have completely different TSSs for each CPU. Otherwise you could have problems if one cpu set the TSS as used or both CPUs went to CP0 with the same PL0 stack.

[kataklinger]

hmmm...could it be possible to have one CPU running in protected mode, and the other running in (un)real mode? (that was my friends original question...)

Could be, but tgen you have problem to synchronize those CPU-s (CPU in ream mode cannot access local APIC for instance).

with the TSS, wouldn't it be possible to have different TSSs for each cpu then?

Well you should have separate TSSs for each processor, or you can get in serious troubles.

[Combuster]

tgen you have problem to synchronize those CPU-s (CPU in ream mode cannot access local APIC for instance).

You can access the Local APIC from real mode, you just modify the base MSR and some MTRRs and you're set.
If you are in unreal mode, its even easier.

[kataklinger]

you just modify the base MSR and some MTRRs and you're set.

Typically, the BIOS (basic input/output system) software configures the MTRRs. The operating system or executive is then free to modify the memory map using the normal page-level cacheability attributes.

In a multiprocessor system, different Pentium 4, Intel Xeon, or P6 family processors MUST use the identical MTRR memory map so that software has a consistent view of memory, independent of the processor executing a program.

So you cannot just change MTRRs. I don't see any need to have one CPU in RM and another in PM, but to introduce troubles.