Where is the GDT?

[Sedition]

I have a few questions.

Where is the GDT stored in memory (physical and/or virtual)?
Can you add GDT entries on the fly if you can access that memory (yes i think)?
How do you get the physical address of something from the virtual address?

[salil_bhagurkar]

You could read the intel manuals and search google for your query.. This is too trivial to challenge anyone's knowledge over here..

[JAAman]

yes, definately get the intel manuals -- im not going to answer these questions, because doing so wont help you at all

if you understood the GDT well enough to use it, then these questions would be obvious (except maybe the second one, but its easily understood if you read the manuals)

i know its a lot, but i really suggest reading volume 3a in its entirety before continuing (pay special attention and reread at least 2 times chapters 2-4)

although you could get away with only reading the first 6 chapters (though section 9.8-9.10 could also be an important read)

[Zacariaz]

i for one have given up understanding the workings of the gdt, or any dt for that matter. i have read the manuals, and i have learned alot, but not regarding this subject.

sometimes trivial questions are asked and wether or not to answer them is of course your choice, but please dont let people look like complete idiots just because there is something they dont understand.

[Combuster]

sometimes trivial questions are asked and wether or not to answer them is of course your choice, but please dont let people look like complete idiots just because there is something they dont understand.

I can hardly say anybody did: the most blunt reply was basically "RTFM & STFW". Unless you have read http://catb.org/~esr/faqs/smart-questions.html you will probably have made that mistake yourself once.

[Gizmo]

I'll answer this one for you, only because I feel sorry for you....
(but you should really read those manuals or else you will be completely clueless- osdev'ing is no place for copy-n-paste programming)

The gdt can be stored wherever you want to stick it in memory.
Just make a structure and give the cpu the pointer to it using lgdt.
All other structures except the ones used in paging must have a segment descriptor (and so do segments) on the gdt that you access using the offset into the gdt structure in bytes.
These structures cannot be in "virtual memory"-use actual offsets so the cpu can get to them since it doesn't use page translation when accessing them.

You must understand that if you don't put forth enough self effort to read the manuals you just wont understand most of this. Now if you read the manual (the one from intel for x86) and don't understand something then we will be glad to help you and we probably won't assume your trying to take advantage of others without doing any real work on your behalf.

[Combuster]

The gdt can be stored wherever you want to stick it in memory.
Just make a structure and give the cpu the pointer to it using lgdt.
All other structures except the ones used in paging must have a segment descriptor (and so do segments) on the gdt that you access using the offset into the gdt structure in bytes.
These structures cannot be in "virtual memory"-use actual offsets so the cpu can get to them since it doesn't use page translation when accessing them.

I really suggest you reread the manuals yourself. Giving the wrong information is IMNSHO worse than giving no information.

The GDT does not essentially reference any other structures. The processor keeps offsets to all current structures in one of its special registers. The only thing that happens is once you select an TSS or LDT, these special registers are loaded from a GDT entry. (Selectors can also be loaded from the LDT) After that, the selectors are essentially no longer needed. Paging structures and the IDT are not referenced by the GDT, actually, the IDT references entries into the GDT. And then there are many more less-commonly known tables that are completely independent of the tables above (MTRR, PAT, etc)

And then the intel manuals state that the address of the GDT and LDT are linear addresses, not physical addresses. It also says that segmentation is layered on top of paging. I.e. the IDT, GDT and LDT are affected by paging and hence do *NOT* live in physical memory. In other words, the processor DOES use page translation when accessing the GDT, LDT, IDT and TSS.

[JAAman]

i for one have given up understanding the workings of the gdt, or any dt for that matter. i have read the manuals, and i have learned alot, but not regarding this subject.

sometimes trivial questions are asked and wether or not to answer them is of course your choice, but please dont let people look like complete idiots just because there is something they dont understand.

the reason i didnt answer the question is, the answers to those questions would not do him any good at all, as there are deeper issues with his understanding (as is evidenced by the questions he asked)

i dont feel that these are trivial questions at all, rather they are very important questions, which is why i feel that answering them will do him more harm than good at this point

there is no way you can understand these things (the entire addressing system -- including paging) without reading chapters 2-5 completely -- that is, rereading every single word many times (and even then, if you didnt read the rest of the book, then you may still have trouble) basically, dont try to understand any of it the first time you read it (as you wont until you finish the book), only start understanding it the second time through, and you should really read it 3-4 times minimum before you actually understand it completely -- especially paging, since the GDT is very simple, once you understand how the CPU uses it (though you will have a lot more trouble if you dont understand RMode addressing)


however, if you really want the answers to those questions, then here they are:

Where is the GDT stored in memory (physical and/or virtual)?

wherever you choose to put it

Can you add GDT entries on the fly if you can access that memory (yes i think)?

yes (sometimes, there are exceptions -- such as not any currently active segment)

How do you get the physical address of something from the virtual address?

that is something which would take about 60 pages to explain properly, but basically, lookup the current relevant segment in the GDT and add the segment base to the offset, then lookup the address in the page tables (as determined by the current paging mode) to find the physical page, then add the in-page offset to find the specific address (see 3A:fig 3-1)

[vhg119]

Where is the GDT stored in memory (physical and/or virtual)?

If you enable paging, I think they live in virtual memory. However, you can map those virtual addresses 1 to 1 onto their physical addresses.

If you did not enable paging, the linear addresses are the physical addresses.

I've read chapters 4 - 7 of the Intel Manual 80386 about twenty times over along with tons of tutorials and articles. I am also still confused by a lot of it. I recommend you don't stop here. Get our explanations, then research a little more until it makes total sense to you.

[JamesM]

vhg: It seems like you don't quite understand it either, from your response!

the GDT lives wherever the hell you put it. When the CPU accesses *ANY* address, it goes through the MMU. So, if you have enabled paging and segmentation, those mappings are applied.

If you load via grub the GDT is *somewhere*, I don't know where and neither should you, replace it with your own ASAP.

[vhg119]

vhg: It seems like you don't quite understand it either, from your response!

Isn't that obvious?

Actually, after I read my post, I realized I didn't do a good job of explaining it.

[SpooK]

The basics of the GDT are usually overlooked by beginners.

The GDT/LDT/IDT are nothing but your basic equivalent of a data structure in a high-level programming language, such as C. You use a special instruction that sets a special register in the CPU, used only for this purpose, to specify *where* in physical memory (or virtual memory if paging is applied) this structure is placed... in other words... you give the CPU a pointer to that memory location.

After that, the CPU uses that *pointer* as a base address to access those structures. The only requirements are that the structure is accessible and contains valid data... otherwise you will find out quickly as to what happens if you violate those requirements.

Now, with that in mind, please go ahead and take the default advice of reading the appropriate manuals.