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Hi,

I am reading the source code of xv6(http://pdos.csail.mit.edu/6.828/2011/xv6.html) recently, which can handle multiple processors. Something confuses me.

In its mpinit function there is a snippet:

It searches for the MP floating pointer structure(the mp variable) and then find whether there is IMCR. And if there is, which means we are in PIC mode, set the IMCR 0x1. What confuses me is the comment Mask external interrupts . From MP spec, I learn that setting the IMCR 0x1 is one step jumping from PIC mode to Symmetric I/O mode, making the CPU receiving IRQs from local APIC, not directly from 8259A PIC. Does this have something to do with masking external interrupts? Do I miss something or there is something wrong with the comment?

Hope someone could help me. Thanks in advance.

Addition:
When boot, the local APIC is software disabled, so some IRQs cannot be handled. Maybe the comment refer to this???

Hi,

The MP tables are basically obsolete and I wouldn't bother with them at all unless you want to support very old machines.
The ACPI MADT Table is really you go-to source of information for configuring a multiple processor system.

Disabling the IMCR (also probably only on very old machines) is really more relevant to when you want to switch from using the 8259 PIC to the IOAPIC.

For my SMP startup I don't worry about any of this (I configure ioapic etc afterwards). All you need from an irq point of view to get smp up and running is some sort of timer (to set delays during the init of the other cores).
You could use the PIT/8259 combination for this or the local apic timer (which requires a bit more prep to determine the frequency).

What is important is to know the topology of the machine from the MADT table and using CPUID then having the local apic on the BSP (boot processor) initiate the trampolines and bring up the other cores.

The ACPI MADT table has a flag (similar to the mp table imcr one) which indicates if legacy PIC needs to be disabled.

Based on that flag I do the IMCR set as well as masking all IRQS on the PIC and then configure the IOAPIC. There could be multiple IOAPICS, once again the MADT table will give you all the details.
Be careful though when you switch from PIC to IOAPIC some of the standard ISA irq numbers might change (IE: IRQ0 = timer might become IRQ2 for example). These "interrupt overrides" are also described by the ACPI tables.

To make things easier for you to implement I would suggest making sure you've fully parsed all these ACPI data tables and have them ready before proceeding with other os tasks.. it will make your life easier from a dev point of view then to have to keep going back and adding little bits to get the info you need. I parse the MADT, MCFG, FACP, HPET, SRAT tables (sometimes they're not all present). There are other tables as well which contain AML instead of just data structures like the DSDT and SSDT tables.. but you don't need that for now.

Thanks for your reply johnsa.

Nice to hear it is outdated. I do get confused when I refer both the Intel manual and the MP spec published in 1997. The Intel manual does not mention what the MP spec describes at all. And actually I am still confused you say that:

What do you set the IMCR for? And if I want to learn the tech used now, should I refer the ACPI spec or something else?

A combination of the ACPI Specification and the articles on the OSDev Wiki right here cover pretty much everything to do with it.
I would start with the ACPI tables as it will give you a good feel for what sort of information is present (even if you don't use all of it to start with) you'll know where to look later on.

http://wiki.osdev.org/ACPI
http://wiki.osdev.org/MADT -- refer to the spec for more detail
http://wiki.osdev.org/Category:ACPI -- this category covers the basic process of finding the various acpi table.

Thanks for your recommendation and patience, joshsa. I will refer the spec and links.

Hi,



If the computer has ACPI then there is no IMCR; and if there is no IMCR you'd be modifying an unknown IO port and can expect unknown consequences.

For rough history (mostly from memory):

• Before about 1994: There was no standard. A few computer manufacturers cobbled together hideous non-standard things; but (even though they used 80x86 CPUs) these machines had special/proprietary chipsets, weren't considered "PC compatible" and required specially designed OSs.
• About 1993: Intel released their 82489DX "external local APIC" and their IO APIC, and created/released the first version of the MultiProcessor Specification to document the "standard" way things would work (or the way it worked for their chipset at least). Their MultiProcessor Specification had multiple different options - the IMCR way was one, "virtual wire" was another. Some motherboards used an IMCR and some didn't.
• About 1995: For Pentium Pro; Intel added the local APIC onto the CPU itself, and broke compatibility with the original MultiProcessor Specification (the AP CPU startup procedure changed). They released a new version of the MultiProcessor Specification to cover that.
• About 1996: Intel "back-ported" the local APIC (and a few other things) from Pentium Pro back into the older Pentium CPU and released "Pentium Processor with MMX" (mostly for people looking at upgrading older motherboards designed for the original Pentium). By this time the "virtual wire" method had begun to dominate, and the IMCR was mostly obsolete.
• About 1996: The first version of ACPI was released. It was hideously overcomplicated so most manufacturers didn't bother with it and those that did screwed it up. Because the IMCR was mostly obsolete ACPI had no reason to support the IMCR.
• About 2000 to now: Computers started to get ACPI "sort of right maybe" (enough to be usable if you're lucky, but you'd better have both a blacklist and a whitelist just in case ).

Cheers,

Brendan

A more professional reply!